In mobile devices such as mobile telephones, display devices that use so-called monolithic technology, in which a drive circuit is formed on a glass substrate, simultaneously with the forming of pixel TFTs (thin-film transistors) have come into widespread use. In recent years, rather than circuits implemented by poly-Si TFTs, circuit implemented by TFTs that use a-Si (amorphous silicon) or oxide semiconductors such as indium gallium zinc oxide (an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O)) have begun being used.
It has been known that, in a drive circuit formed using the above-noted monolithic circuit technology, the threshold voltage of the TFTs might change due to aging or exhibit temperature dependency. In particular, there are cases in which a shift register circuit used in a scanning line drive circuit can have the following problem.
Specifically, in a shift register circuit, the gates of output TFTs used to drive the scanning lines operate with a voltage raised to a high voltage by bootstrapping, and diode-connected TFTs are used to pre-charge the gate electrodes and also so that there is no leakage at the time of boosting.
When using a diode-connected TFT, the pre-charge voltage is a value that is dropped by the amount of the threshold voltage of the TFT. Because a TFT that uses a-Si or an oxide semiconductor such as indium gallium zinc oxide exhibits a characteristic of variation in the threshold voltage because of the voltage stress applied to the gate electrode, the characteristics deteriorate with the passage of time, and the pre-charge voltage decreases commensurately. When the pre-charge voltage decreases, the voltage boosted by bootstrapping also decreases, the driving capacity of the output TFT decreases, and the output waveform becomes distorted. With further deterioration, the output voltage decreases and the shift register operation becomes unstable. This problem can be solved by, for example, using large TFTs that take into consideration the deterioration of characteristics. In this case, however, there is a problem of the surface area of the circuit increasing.
An example of a shift register circuit that seeks to solve such problems is described in Patent Document 1. Each stage of the shift register circuit shown in FIG. 2 of Patent Document 1 (which shall, along with the present invention, be referred to hereinafter as a unit shift register circuit) has a first input Rn−1 connected to the output of the previous stage, a drive transistor Tdrive that couples the first clock power line voltage Pn to the output of that stage, a compensation capacitor C1 for the purpose of compensating for the influence of the parasitic capacitance of the drive transistor, a first bootstrapping capacitor C2 connected between the gate of the drive transistor and the output of that stage, and an input transistor Tin1 (setting TFT), controlled by the first input Rn−1, for the purpose of charging the first bootstrapping capacitor C2. Additionally, each stage of the unit shift register circuit has an input section 10 having a second bootstrapping capacitor C3 connected between the gate of the input transistor Tin1 and the first input Rn−1 and which is coupled to the output Rn−2 of the stage two stages before.
In the unit shift register circuit described in Patent Document 1, by using two bootstrapping capacitors, the circuit is desensitized to the level and variations of the threshold voltage, enabling implementation using amorphous silicon technology.